Field programmable logic and in particular, field programmable gate arrays (FPGAs), have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, such reconfigurable arrays have been used to enhance customer product flexibility in ways that no other technology can currently match.
Microprocessors have traditionally been used to satisfy time to market and end product flexibility needs. This solution may not meet performance constraints and lacks the concurrency possible in an unconstrained hardware design. Typical design processes, therefore, reach a point where the overall design is partitioned into hardware and software components. An interface is defined and the design process continues along two parallel paths. Sometime later, the software and hardware components must be integrated. Problems usually develop at this point because of interface misinterpretation or partitioning that cannot meet design requirements. This impacts the hardware, the software and the schedule. If the hardware design is realized in programmable logic, the hardware can be manipulated as easily as the software.
Products which adapt to the end user's particular requirements, through self-directed or end user directed reconfiguration, are becoming more prevalent. As the number of modes of operation increases, mode-specific hardware becomes a less cost-effective solution. In the case where the end user is truly directing the adaptation, predetermined hardware solutions become unacceptable. Reconfigurable logic enables design solutions where dynamic hardware/software re-partitioning is possible.
Programmable logic not only vastly improves the time necessary to implement a static design, but significant time to market and product feature benefits can be realized when hardware can dynamically be altered as easily as software.
To reduce design cycles, designers have also turned towards high level design languages (e.g., HDL) and logic synthesis tools. Many programmable logic solutions are poorly suited to this design methodology, however. An incompatibility exists between logic synthesis algorithms originally developed for gate-level design and the block-like structures found on many programmable logic devices. This can result in significant under utilization or degraded performance. In either case a more expensive device is required. Real gate-level programmable devices are ideally suited to this design methodology.
When schematic-based design methods are used, some programmable logic solutions impose significant constraints on design implementation to ensure satisfactory results. This imposition tends to bind the design to a particular programmable device and requires a significant learning investment. Any design specification changes which impact design decisions made to fit this imposed structure can have disastrous effects on utilization and performance and can potentially require a more expensive device or even a costly redesign. Gate-level programmable devices, coupled with sophisticated, timing-driven, implementation tools, minimize device-specific optimization.
Any design process includes a significant amount of learning. Usually engineers spend most of this time learning about product requirements or prototyping critical portions of the design to prove implementation feasibility. Many programmable logic solutions are not "push button". Time must be spent learning programmable device architecture or implementation tool quirks. Worse yet, the design may require modification or manual component placement to meet design targets. This increases the cost and time to market.
The discipline of multimedia signal processing typifies the challenges discussed hereinabove. Various emerging and evolving multimedia standards continue to create substantial confusion in the design of appropriate IC (and systems incorporating ICs) architecture(s). The current "solutions" to these problems can broadly be characterized as:
dedicated multiple chipsets, along with some number of interface chips; and PA1 programmable engines, specific to a particular standard, along with some number of interface chips. PA1 audio and/or video CODECs for interfacing to external analog multimedia signals; PA1 phase locked loop (PLL) circuitry to reduce skew within various blocks within the IC chip and to synchronize to off-chip clock circuitry; PA1 a programmable, fast serial interface core; PA1 a programmable CPU interface core; PA1 a programmable memory interface (PMI) core; and PA1 power-down circuitry, in combination with one or more of these additional cores, to provide power and/or processing savings when a given one of the cores is not in use.
Each of these "solutions" requires multiple chips, and either a very expensive custom system/board combination of chips for each application or an inefficient use of multiple chips to meet a specific application. Hence, there is a need for a solution to facilitate multimedia system or subsystem design using a single IC chip which is adaptable (or readily configurable) to a variety of standards.